| 摘要 |
PURPOSE:To realize the sequential memory reading with no intervention of a CPU and also to shorten the time needed for a test, by using an I/O controller, an incrementer and plural switching devices. CONSTITUTION:The switching devices 11 and 12 are turned off and on respectively in a test mode and therefore the control of an I/O 1 is separated from an I/O decoder 2 and shifted to an I/O controller 10 which connects the I/O 1 and a data bus 14. While the prescribed value is set to the counter of an incrementer 9 as its initial value. Then the numeric value '1' is successively added to the counter of the incrementer 9 synchronously with the internal clock of a system. The output of the incrementer 9 is is applied onto an address bus 13 as an address signal via the device 12. This address signal is decoded by a ROM decoder 6 and the contents of a ROM 5 are successively head out and then supplied to the I/O 1 via the bus 14. Thus the memory test time can be shortened. |
