发明名称 ARITHMETIC CHECKING CIRCUIT
摘要 PURPOSE:To improve the reliability of arithmetic processing by checking errors without fail if arithmetic data includes a checking bit. CONSTITUTION:If the arithmetic data 101a or 101b includes the check-bit, an error suppression signal 107 or 108 corresponding to the data is turned off. Therefore an arithmetic checking part 1 corresponds to an error signal 105 or 106. Accordingly the result that the arithmetic data 101a or 101b is checked is transmitted as an error signal 111. If the arithmetic data 101a or 101b excludes the checking bit, the error suppression signal 107 or 108 corresponding to said data is turned on to suppress the error signal 105 or 106. At that time the error signal 111 never shows the presence or absence of an error.
申请公布号 JPS62239239(A) 申请公布日期 1987.10.20
申请号 JP19860083499 申请日期 1986.04.10
申请人 NEC CORP 发明人 KASUGAI HIROFUMI
分类号 G06F11/00 主分类号 G06F11/00
代理机构 代理人
主权项
地址