发明名称 CLOCK REGENERATING CIRCUIT
摘要 PURPOSE:To lower the frequency of a reference signal generating circuit by setting the frequency division ratios of the 1st and the 2nd variable frequency dividing means according to the result of phase comparison of a phase comparing means. CONSTITUTION:Edge information extracted by a D flip-flop 16 and an exclusive OR circuit 18 is supplied to CK terminals of D flip-flops 19 and 20 to latch the output of a frequency divider 15 and the Q output of the D flip-flop 19. The Q outputs of the D flip-flops 19 and 20 are supplied to a frequency division ratio setting circuit 21. The frequency division ratio setting circuit 21 outputs frequency division ratio information on the basis of the Q outputs of the D flip-flops 19 and 20. The in-phase output of a reference signal generating circuit 11 is supplied to a counter 12 and the negative-phase output is supplied to a counter 13; and overflow signals from the counters 12 and 13 are selected by a selecting circuit 14 and a selected signal is frequency-divided by the fre quency divider 15. Consequently, the frequency of a reference frequency from a reference signal generating means is lowered.
申请公布号 JPS62239738(A) 申请公布日期 1987.10.20
申请号 JP19860084704 申请日期 1986.04.11
申请人 SANYO ELECTRIC CO LTD 发明人 MIZUTANI YOSUKE
分类号 H04L7/033;H03L7/06;H03L7/08;H04L7/02 主分类号 H04L7/033
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