Television display system with flicker reduction processor

摘要

The field rate of a video input signal is doubled by storing each field in a memory and recovering each stored fields twice so as to repeat each field and thus reduce flicker. To ensure that even fields overlay even fields, odd fields overly odd fields and that all pairs of even and odd fields are interlaced, a timing unit provides a double field rate control signal to the memory having a waveform that repeats on a two-field basis and supplies a double field rate vertical synchronizing signal to a display having a waveform that repeats on a four-field basis. Registration of images is enhanced further by means of a vertical scan generator having a constant retrace time, a fixed retrace level and employing DC coupling thereby avoiding raster shift which otherwise could occur as a result of the use of non-equidistant vertical synchronizing pulses.