Integrated verticle NPN and vertical oxide fuse programmable memory cell

摘要

A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.