| 摘要 |
PURPOSE:To perform chip selection access at a high speed and to shorten the output floating time by producing an internal circuit control signal from the chip selection input signal at a higher speed in an inactive mode than an active mode of a semiconductor memory and then producing an output transistor control signal at a high speed in an inactive mode. CONSTITUTION:The gate width/gate length ratio of an inverter 2 is set at 1:10, for example, between a P-channel type MOS transistor TR and an N-channel type MOSTR. While a 10:1 ratio is set for an inverter 3. As a result, the internal circuit control signal, the inverse of CS is fast activated in an active mode of the chip selection input signal, the inverse of CS. Then the output transistor control signal, the inverse of CS'' is fast inactivated in an inactive mode of the chip selection input signal. Thus the chip selection access is carried out at a high speed and at the same time the output floating time is shortened.
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