| 摘要 |
PURPOSE:To improve both the yield of chips and the reliability of a random access memory RAM by sharing a random address generator with an address register required for normal operation and also producing the generation and compression of test data via the same circuit. CONSTITUTION:A random address generator 1 sets external address signals A0-Aalpha-1 to a register in a normal mode by a mode selection signal M to output them as they are as internal address signals B0-Balpha-1. In a test mode, pit patterns are outputted periodically to the signals B0-Balpha-1. A write signal In and the write/read signal OUT are outputted to a memory cell which receives access by the signals B0-Balpha-1 via a RAM consisting of an address decoder 2, a memory cell array 3 and a write/read part 4. A data compression/generation device 5 fetches the signal OUT and at the same time outputs a random test write signal R to a multiplexer 6. Then an external write signal D and the signal R are outputted in a normal mode and a test mode respectively.
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