| 摘要 |
A memory cell is provided having reduced read and write times, and a large current dynamic range between the standby mode and the read mode. A pair of cross-coupled NPN transistors operating in the inverse mode have their emitters coupled to a word line and their collectors coupled to receive a supply voltage by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive the supply voltage.
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