| 摘要 |
PURPOSE:To complement a defect where a hardware scale is expanded while utilizing the fast operability of a parallel/parallel multiplier, by dividing two input data into higher and lower orders respectively carrying out multiplication for four times, and summing the products thus obtained. CONSTITUTION:A correction circuit 3 divides a multiplicand X into the higher order data Xh or lower order data X1 in response to a control signal C1 to correct them to Xh' or X1' and selects and outputs one of them. While a correction circuit 4 divides a multiplier Y into the higher order data Yh or lower order data Y1 in response to a control signal C2 to correct them to Yh' or Y1' respectively and selects and outputs one of them. The outputs Xh'.Yh', Xh'.Y1', X1'.Yh' and X1'.Y1' of a multiplier 5 are supplied to a correction circuit 6 to be corrected to (Xh'.Yh')', (Xh'.Y1')', (X1'.Yh')' and (X1'.Y1')' respectively in response to a control signal C3. These corrected outputs are temporarily stored in a register 7. An adder 9 adds together the outputs of both register 7 and 8 and the result of this addition is stored in the register 8.
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