| 摘要 |
<p>PURPOSE:To facilitate the correction of the deviation of an output signal due to the resistance error, to reduce the test cost and the chip area by providing >=1 auxiliary gate to a drain diffusion layer of a switch FET selecting resistors of a ladder resistance circuit and using a signal inverted to a signal of a main gate to drive the auxiliary gate. CONSTITUTION:The auxiliary gates 11, 12, 13 are provided to a drain diffusion layer 2 via an insulation film SiO2 10 as soon as the main gate 9 controlling a channel region 8 between the drain diffusion layer 2 and a source diffusion layer 3 is formed. In driving the auxiliary gates 11,12, 13 by a signal inverted to a signal of the main gate, an inverted layer is formed to the surface of an N<-> layer 2 and its on-resistance is increased. The width of the inverted layer is controlled by number of the auxiliary gates to be driven and the depth of the inverting layer is controlled depending on the signal level and the on- resistance of each FET is controlled optionally. Thus, the deviation of the output due to the error in the resistance of the ladder type resistance circuit is corrected easily by selecting the auxiliary gate driven by each FET for the switch selecting the resistance.</p> |
