发明名称 BLOCKING ADDRESSING DEVICE FOR MULTIDIMENSIONAL ARRANGEMENT
摘要 PURPOSE:To realize the blocking mapping to a one-dimensional storage space of a multidimensional arrangement by generating a block address, and an in- block address from the sum of products of a subscript value of each dimension and a subscript size of each dimension, and from its subscript value, respectively. CONSTITUTION:In case of referring to an array element A (i, j), subscript values (i), (j) of each dimension are held in registers 11, 12, respectively, and a value which raised fractions of the quotient obtained by dividing a subscript size of the subscript (i) by 2N is held in a register 13. Also, the lower N bits of the registers 11, 12 are sent as they are to an output register 16, as in-block address generating bits of a one-dimensional storage space. On the other hand, the upper bits of the registers 11, 12 are sent to a multiplier 14 and a full adder 15 in order to generate a block address and calculated with a value of the input register 13, and an output of the full adder 15 is sent to an output register 13, and an output of the full adder 15 is sent to an output register 16 as a block address of the one-dimensional storage space.
申请公布号 JPS62235660(A) 申请公布日期 1987.10.15
申请号 JP19860078656 申请日期 1986.04.04
申请人 NEC CORP 发明人 NISHI NAOKI
分类号 G06F12/02;G06F12/00;G06F12/08;G06F12/10 主分类号 G06F12/02
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