| 摘要 |
PURPOSE:To obtain a full subtracter which is optimum for constituting a subtracter and divider of a higher speed, by using a CMOS composite gate, and decreasing the number of logical gate stages generated by a delay time. CONSTITUTION:When input signals A, B, and Ci are simultaneously inputted, the signals A, B, and Ci are simultaneously obtained by inverters 5, 6 and 7, respectively. Also, six signals A, B, Ci, the inverse of A, the inverse of B and the inverse of Ci are inputted to logical gates 1-4, therefore, a difference output signal D is obtained by a delay time of two stages of gates, of one stage of the inverter and one stage of the logical gate (1 or 2). Moreover, a borrow output signal Co is also obtained in the same way by a delay time of two stages of gates, of one stage of the inverter and one stage of the logical gate (3 or 4). Accordingly, the delay time of a full subtracter is shortened to about 1/2.5 of a conventional time, together with the difference output signal D, and the borrow output signal Co. |
