| 摘要 |
<p>A fast pipeline adder (20) comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders (21-1). In another embodiment, modified adders are employed which accept two carry inputs and develop two carry outputs. The resulting number of individual cells is reduced to approximately half of those in the prior embodiment. In still another embodiment, switch means are included in each cell (114) to delete the reclocking and in still another embodiment, the adders in the diagonal of the pipeline adder (20) are provided with additional inputs to permit use of the pipeline adder in recursive addition applications. In still another embodiment, the cells are permitted to output the inverse of the intended signal, reducing thereby the physical realization of the cells and increasing the speed of the cells.</p> |
