High speed and high efficiency layout for dram circuits

摘要

A dynamic random access memory (DRAM) array combining metal word lines and folded bit line architecture. Multiplexed switching of the bit lines is utilized to make connection to the sense amps. The word lines connect to every fourth access transistor in a column with twice as many word lines employed as in prior art arrays. The use of folded bit lines reduces the effects of noise on bit line sensing while the metal word lines increase speed by several orders of magnitude. The sense amps are disposed between blocks of memory cells and sense every other bit line. Column decoders are placed between rows of sense amps with row decoders and drivers at the end of the blocks of cells.