Memory for a digital data processing system including circuit for controlling refresh operations during power-up and power-down conditions

摘要

A memory for use in a digital data processing system, the memory including a memory controller and one or more memory arrays. A memory array performs refresh operations transparently to the memory controller, but in synchronization with a system timing signal while it is receiving normal system power. A memory array also includes asynchronous refresh circuitry for controlling refresh while the system power is interrupted and the array receives no system timing signal. When each refresh operation occurs during power interruption, the asynchronous refresh circuitry tests the condition of the system power supply. Since refresh operations are transparent to the memory controller, the memory array indicates when the memory operations are completed. If the memory operation is a read operation, the memory controller then controls the transfer of data from the array to the controller.