| 摘要 |
PURPOSE:To reduce a synchronization locking time by changing a count prescribed number of phase difference information of a counter means so as to obtain a stable output signal when out of synchronism is detected by an out of synchronism detecting means. CONSTITUTION:A counter 17 of the out of synchronism detection circuit 14 counts an output of an AND gate 16 and when an output of an exclusive OR circuit 15 exceeds a prescribed value until it reaches an H level, an overflow signal S3 is outputted. A counter 18 counts the overflow signal and when a prescribed value is exceeded within a time predetermined by a counter circuit 19, a signal is fed to a control signal generating circuit 20 to invert the level of the control signal to the H level. The L level output is fed continuously to the counter IC 21 from a phase comaprator 12 and the count reaches 0111, then an output of an AND gate 23 goes to an H level, an output of an AND gate 25 reaches an H level and an output of a NOR gate 28 goes to an L level, then outputs 34,35 of an up-down ocunter 13 go both to an L level, and the frequency division ratio of a programmable frequency divider 11 is set to 1/(N+1). |
