| 摘要 |
PURPOSE:To facilitate extremely handling without the need for manual logic conversion by discriminating the logic of received subcode data and a synchronizing signal, applying a logical conversion in response to the result of discrimination and inputting the subcode data and the synchronizing signal after logical conversion to a demodulation circuit. CONSTITUTION:A subcode frame synchronizing signal S SYNC inputted to a logical discrimination circuit 46 is converted by a buffer 40 to be at V CC level when logic level is 'H' at to be 0 level when 'L' level, then the result is integrated by a low-pass filter comprising a resistor 41 and a capacitor 44 and compared with a reference voltage by a comparator 45. When the result of discrimination S CONT of the circuit 46 is at 'L', a logical conversion circuit 51 acts as a non-inverting buffer. When the S CONT is at 'H', a logical conversion circuit 51 acts as an inverting buffer. Thus, reception data and the synchronizing signal S SYNC, S DAT, S CK and S BCK are converted into positive logic by EX-OR circuits 47-50 and sent to a demodulation circuit 16.
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