| 摘要 |
PURPOSE:To speed up the element-data transfer between vector registers by providing two pieces of read-address setting means per a vector register, and an element transfer means between the vector registers. CONSTITUTION:The followings are comprised in the title device: vector registers 100 and 101, a vector buffer register 102, the first read address registers 110 and 111, a read/write address register 112, the second read address registers 120 and 121, write address registers 130 and 131, the first read address selection circuit 140 and 141, read/write address selection circuit 142, the second read address selection circuit 150 and 151, write address selection circuits 160 and 161, the first read data 170 and 171, the second read data 180 and 181, and an element-data-input selection circuit 200. The registers 100 and 101 hold plural element data that are respectively arranged in order. In such a case, the element data are transferred from the first vector register to the second vector register in accordance with a vector instruction. |
