| 摘要 |
PURPOSE:To connect a device that needs a high-speed processing without increasing the number of pieces of scanning units by shortening the vacant time between two DMA transmission by using plural DMA holding latches. CONSTITUTION:Direct memory access DMA holding latches 56, 57, registers 59, 60 to store the line address at the time of DMA request issuing, transmission data registers 63, 64, and registers 66, 67 to fetch numbers corresponding to DMA holding beats at the time of completing the DMA transmission, are provided in, for instance, two sets. By increasing the number of latches and registers in accordance with the number of lines to be scanned, the line speed, and the rate of use of a DMA bus, it is made possible to connect a line whose speed is even higher. It means that after the completing of the DMA transmission through a line A, a DMA request is issued through a line B without waiting for the postprocessing (updating of memory address, data counting, etc.) for the DMA through the line A, so that the vacant time between the DMA transmissions is shortened. |
