发明名称 TESTING SYSTEM FOR INPUT/OUTPUT DEVICE
摘要 PURPOSE:To perform the test of a proper hardware by the optimum pattern, by returning an input/output instruction and an input/output data in the generating time of an error, after saving and storing them in an input/output device, and performing an execution again by a software. CONSTITUTION:When the error is generated, an error detecting part 700 detects the error, and informs it to a processing part 400. The processing part 400, after locking 900 an input/output instruction storing area 600 which stores the instruction and the data of an error factor, and an input/output data storing area 500, informs the completion of the saving and the storage of the instruction and data at the generating time of the error, to a CPU through a saving and storage informing part 100. The CPU unlocks the locks of the areas 600 and 500, and sends the transfer instruction of a stored instruction and data to a main storage device, to a saving and storage data read out decoding part 200. By informing a decoded instruction to the processing part 400 by the decoding part 200, the processing part 400 unlocks 800 the locks of the areas 600 and 500, and sends the instruction and the data to the main storage device through a data transfer part 300, and performs again the execution of the instruction and the data by the software.
申请公布号 JPS62231359(A) 申请公布日期 1987.10.09
申请号 JP19860073962 申请日期 1986.03.31
申请人 NEC CORP 发明人 KIMIJIMA KOJI
分类号 G06F13/00;G06F11/22 主分类号 G06F13/00
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