| 摘要 |
PURPOSE:To attain consecutive operation by high speed writing and idle area detection by forming a means for detecting at the time of data writing that a region with stage number larger by one than that of a data idle area to be detected by an FIFO circuit is an idle area. CONSTITUTION:The circuit consists of a NOR gate inputting signals Q1-Qn going to a high level when a data exists in the 1st-5th stages of the FIFO circuit and outputting a signal Q0 and a D.FF circuit inputting the signal Q0. In this circuit, the clock of the FF is used as a write signal WR in synchronism with the system clock to latch a high level of the signal Q0 before the signal Q1 goes to a high level. Thus, the presence of an idle area larger than the idle area to be detected by one stage is represented until the next data are written and a margin is provided for the detection time. Thus, high speed data write and the consecutive operation of the idle area detection are attained.
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