| 摘要 |
PURPOSE:To complete the read of digital information to a latch circuit by synchronizing a latch inhibiting signal with a clock pulse and generating a latch signal with AND between the latch inhibiting signal and the lock pulse synchronized with each other. CONSTITUTION:A CPU 10A outputs not only a read signal RD but also a latch inhibiting signal LE preceding the signal RD. The latch inhibiting signal LE is synchronized with the fall timing of a clock pulse (a) by a synchronizing circuit 14 to obtain a signal LE'. AND between the synchronized latch inhibiting signal LE' and the clock pulse (a) is operated by an AND circuit 22, and the output is a latch signal e'. Since the read signal RD is outputted from the CPU 10A thereafter, contents of a latch circuit 20 are read into the CPU 10A through a data bus by the read signal RD. Since the latch signal e' has always the same pulse as the cock pulse (a) and is synchronized with the clock pulse (a), contents of a counter 18 are transferred to the latch circuit 20 by the latch signal e' having a complete width. |
