| 摘要 |
PURPOSE:To reduce a delay time of a logic circuit constructed to be accessible directly from an external terminal, by using an input buffer element as an input terminal and an input buffer circuit at the time of testing the logic circuit from the external terminal, aud by using an output buffer element as an output terminal and an output buffer circuit at that time. CONSTITUTION:When a circuit 5 is tested by a control input terminal 3, a low level is impressed on the control input terminal of a 3-state circuit 9 aud a terminal 2 is put in an input mode. Meanwhile, a high level is impressed on the control input terminal of a circuit 6 and a signal impressed on the input thereof from the output of a circuit 10 is obtained at the output of the circuit 6. As for a 3-state circuit 8, a high level is impressed on the control input terminal thereof and an output signal of the circuit 5 is obtained at a terminal l. When a logic circuit is in the state of ordinary operation, the 3-state circuit 9 conducts an output buffer operation and an output of a circuit 4 appears at the terminal 2. Meanwhile, the output terminal l of the 3-state circuit 8 operates as an ordinary input terminal. Moreover, an output signal of the circuit 4 is outputted at the output of the circuit 6. By this constitution, the increase in a delay time of the logic circuit is prevented without increasing the number of input/output terminals. |
