| 摘要 |
PURPOSE:To attain the fast bus arbitration by supplying the bus request signal received from a bus master and the priority designating signal received from a priority designating circuit to a memory storing the data on the bus use permission signal as the address signals. CONSTITUTION:The bus masters 12a-12n which try to transmit data via a system bus 11 output the bus request signals. These request signals are supplied to a ROM 15 storing the data on the bus use permission signals as address signals together with the output signal (priority signal) of a priority designating signal 16 consisting of a counter. Then only the bus master that is designated by the output data of the ROM 15 can secure the using right of the bus 11. In this case, another bus request is accepted by the priority signal applied to the ROM 15 even though the bus request signal of a certain pattern is supplied to the ROM 15. Then the bus use permission signal is outputted to said bus request from the ROM 15. |
