发明名称 GRAPHIC ACCELERATOR PIPELINE STRUCTURE FOR WORK STATION
摘要 PURPOSE:To attain a graphic processing with the same hardware unit by applying the algorithm of a simple equation to the executing procedure of a multiplication/division circuit and using it to the operation of a graphic function. CONSTITUTION:An accelerator is constituted of an ALU, plural LSI having the processing procedure of simple equation, a RAM storing a microprogram, a trigonometrical function table, a curve function table, a cache memory, an FIFO, a pipeline bus 4 and a common bus 5. These accelerators 10-12 are connected with each other via both buses 4 and 5. The microprograms of different functions (curve generation/paint-out processing and perspection conversion processing) are loaded to the RAM of each accelerator via the bus 5 and in the initial process. Each accelerator gives the dividing process to said processing in terms of pipeline.
申请公布号 JPS62229375(A) 申请公布日期 1987.10.08
申请号 JP19860040807 申请日期 1986.02.26
申请人 GOTO HIDEO 发明人 GOTO HIDEO
分类号 G06T1/00 主分类号 G06T1/00
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