| 摘要 |
<p>Method of controlling path memory in a Viterbi decoder wherein, when a plurality of decoding steps are required for the trace back up to the final stage of the surviving path, decoded data as many as the decoded steps consumed for the trace back are outputted from a path storage circuit to thereby determine the decoded data. During the tracing back, furthermore, the condition shift data are synthesized over a plurality of time spans to trace back to the final stage of the surviving path through a plurality stages of jump backs by one time of memory access, making it possible to realize a high-speed decoding operation.</p> |
