| 摘要 |
<p>A Global Position System (GPS) receiver is disclosed which includes an RF converter and quadrature digitizer implemented in hardware and a signal processor including a computer, code generator and preprocessor. The preprocessor has a divide by 1,2,3 divider for controlling the code generator so as to provide I,Q early, prompt and late digital signals of 0.5 chip separations to the computer for tracking code phase, carrier phase/frequency and signal amplitude. This structure eliminates the need for numerically controlled oscillators implemented in hardware while maintaining accurate performance.</p> |
