| 摘要 |
PURPOSE:To enable the use of a small capacity low speed vector memory and to enable the stable operation of a LSI chip being a simulation object, by forming a lead signal and a second reference clock, etc. on the basis of a reference clock by a control part according to a hardware system. CONSTITUTION:When a start signal X is applied from a host calculator 1, the frequency of a reference clock phiC is divided by a control part 4 to form a second reference clock CLK and a read signal RD having phase difference such as one cycle of the clock phiC with respect to said clock CLK. Simulation input is read from a vector memory 3 corresponding to the signal RD to be supplied to a LSI chip 2 controlled by the clock CLK. By the formation of the clock CLK and the read signal RD by a hardware, a reference clock is stabilized and formed by a forming source different from an input vector train forming source and the phase difference thereof can be set to a predetermined value without increasing vector quantity. By this constitution, the capacity of the vector memory can be reduced and the speed thereof is decreased and LSI being a simulation object operates stably.
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