A comparator for comparing differential input signals and method therefor.

摘要

A high speed two micron CMOS comparator uses an input differential stage (11) having feedback current mirror loads (18, 20) providing high speed current signals to an output cascode stage (28). Current mirror arrangement provide fast signal propagation through the comparator. Hysteresis is established by the output of the comparator positively fedback through a similar feedback differential stage (42) superimposing controlled current signals into the cascode stage. Hysteresis of the output signal respecting a differential input signal is controlled by the ratio of bias currents of internal current sources which ratio is relatively insensitive to temperature changes.