发明名称 PEAK HOLDING CIRCUIT
摘要 PURPOSE:To enhance time resolving power while enabling the accurate detection of a peak value, by discharging a holding value after a predetermined time is elapsed from the point of time when an input pulse wave-form becomes smaller than the peak value being held. CONSTITUTION:When an ultrasonic echo is inputted to a transducer 14, said echo is supplied to the terminal of a peak holding circuit 20 through an amplifier 15 and a full-wave rectifier circuit 16. In the circuit 20, a signal having the almost the same wave-form as that of the inputted ultrasonic echo appears at the output terminal of an operational amplifier 2 and a peak value is held to a condenser 11 through a diode 3 and a protective resistor 4. This peak value is compared with the wave form of the inputted ultrasonic echo by a comparator 8 and, when the input wave form becomes lower than the peak value, comparing output comes to 'H' and is integrated by discharge signal generating circuits (9, 11) and, after a predetermined time prescribed by the time constant thereof, a discharge signal is sent out. By this mechanism, MOSFET 12 turns ON and a discharge circuit is closed and the peak value held to the condenser 5 is discharged quickly.
申请公布号 JPS62228171(A) 申请公布日期 1987.10.07
申请号 JP19860069745 申请日期 1986.03.29
申请人 TOSHIBA CORP 发明人 KOSUGE HIDEO
分类号 G01R19/04 主分类号 G01R19/04
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