FULL FLOATING POINT VECTOR PROCESSOR

摘要

The processor includes a master processing unit (12) having DMAI/O means (48), a wide bandwidth data memory (14), an address generator (28) operative to generate addresses for data loaded in the data memory, a concurrently operating pipeline control sequencer (31) operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit (36) responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator (28). the pipeline control sequenncer (31), and the master processing unit (12) are configured in parallel. The address generator (28) includes means operative to provide pipeline input and output data dependent address generation.