| 摘要 |
PURPOSE:To obtain a synchronizing output at a minimum of one clock by providing a delay circuit retarding a time corresponding to a preset time of a flip-flop and two flip-flops sampling and synchronizing the leading from logic 0 to logic l and the leading from logic l to logic 0 in an asynchronizing input. CONSTITUTION:When an asynchronizing input D changes from 0 to 1 in a period of a setup time Ts, since a master rest MR1 of a flip-flop l is asserted by a delay time Td, the input is sampled at the leading of S2 not being S0 of a clock CP, the clock becomes a clock signal of a flip=flip-flop 3 aud logical 1 is outputted. Further, the data is changed before the period of the setup time Ts, the data is sampled at the leading So. When logical 1 is given to an asynchronous input B of the flip-flop 2, the flip-flop 2 is set after the delay time Td. When the input is changed to logical 0, a flip-flop output T1 is reset iustantly, but the output T2 holds logical l until the flip-flop 2 is sampled by the same condition as the timing of the sample of the flip-flop 1, and when logical 0 is sampled by the clock CP, the flip-flop 3 is reset to make the synchronizing output T3 zero. |
