| 摘要 |
PURPOSE:To perform a transfer operation synchronized with the state of an output side in a memory, and to prevent the omission or the overlapping of a bit of readout information, by detecting the completion of thc readout of all of the contents of registers on the output side, and transferring a bit of information of one line from a memory cell array to a data register by the above detected signal. CONSTITUTION:Assuming that eight bits of information can be stored in a data register 3b, and after a counter circuit 6 counts eight clock signals ch, a control circuit 7 generates a write control signal, and interrupts a write operation to a memory cell array 3a, and after completing the transfer of the bit of information of the next line from the 3a to the data register 3b, a control is performed so as to restart the write operation of an input signal to the memory cell array 3a. Since a period until the content of the next line arrives, is a non-display period including a displaying synchronizing signal R part, the content from the memory cell array 3a is transferred to the register 3b in the period. After the completion of the transfer operation, by switching a switch ll so as to set an output from the second storage element as an input to the memory cell array 3a, it is possible to prevent the omission of a bit of input information due to thc transfer operation, and simultaneously, the transfer of the bit of information to the resister 3b as an output buffer, can be performed exactly.
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