发明名称 BIT LINE EQUALIZER FOR SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To coincide each prescribed capacity ratio of a timing generator an address buffer, and a word driver with each other by constituting a timing generator of input/output gates, a delaying line between both gates, an inverter circuit to add a gate capacity and the like. CONSTITUTION:A timing generator is formed of an input gate 3 of a depletion mode high electronic mobility electric field effect transistor (HEMT) for a load and an enhancement mode HEMT, and a same output gate 4. Between gates 3 and 4, a delaying line 1 to give a wiring capacity 1c and an inverter circuit 2 to add a gate capacity 2c as well as the gate 3 are connected. In accordance with these capacities 1c and 2c, the ratio of the wiring capacity load and the gate capacity load of the timing generator can be made coincident with the same ratio from an address buffer to a word driver. At the time of the increase and decrease in an electric current due to the variance between wafers and the increase and decrease in a gate capacity, the timing is compensated and an access time due to a it line equalizer is shortened.
申请公布号 JPS62226491(A) 申请公布日期 1987.10.05
申请号 JP19860067365 申请日期 1986.03.27
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 NOTOMI SEIJI
分类号 G11C11/34;G11C11/41;H03K5/13;H03K5/135 主分类号 G11C11/34
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