发明名称 CONTROL SYSTEM FOR INTER-PROCESSOR TRANSFER OF DATA
摘要 PURPOSE:To attain the simple transfer of data by preparing both master and slave processors to secure the bidirectional transfer of data between both processors so that the data transfer request is controlled by the master processor. CONSTITUTION:Data are transferred between a master processor MP and a slave processor SP. Then the master data transfer means 3-1-3-n and the slave data transfer means 6-1-6-n can transfer data in both directions via the data transfer paths SP-1-SP-n which are set statically. Furthermore a master control means 2 set at the MP side controls all data transfer requests given from both processors MP and SP.
申请公布号 JPS62226265(A) 申请公布日期 1987.10.05
申请号 JP19860069183 申请日期 1986.03.27
申请人 NEC CORP 发明人 HAMAGUCHI KAZUHIKO
分类号 G06F15/16;G06F13/38;G06F15/177 主分类号 G06F15/16
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