| 摘要 |
PURPOSE:To enhance the throughput of a system by halving the time of possession of a system bus at the time of data transfer. CONSTITUTION:At the time of outputting odd number-th data, clock is inputted to a latch 4 by gating the output of AD0 and the inverse of WRITE signal with an AND circuit 10 and data are held. At the time of outputting even number-th data, the output of AD0 inverted by an NOT circuit 9 and the inverse of WRITE signals are gated with an AND circuit 12 to make it the inverse of WRITE signal to a memory, and held temporarily in a control buffer 13. The inverse of HOLDREQ signal is sent to a CPU15, and after the inverse of HOLDACK signal which is an answer signal, becomes low level, the inverse of WRITE signal to a memory held by the control buffer 13 and 16-bit data held by a bus buffer 7 are outputted on a system but 3. |
