发明名称
摘要 PURPOSE:To convert parallel data into series data easily by using general-purpose CPU by latching the parallel signal from an information processor in a latch circuit and by converting the parallel signal into a series signal successively and then outputting it while a counter counts up and resets once. CONSTITUTION:Data collection station 10 and terminal device 20 are connected together via data transmission lines l1 and l2 and data from terminal device 20 is collected at collection station 10. Clock pulses from the clock oscillator of this collection station 10 are transmitted to terminal device 20 and photocoupler PC of terminal device 20 is put into operation. Every time counter 21 of terminal device 20 is made to count up and reset once with those clock pulses, an output signal is generated at terminal Q4 to control information processor 22, whose parallel output is supplied to input terminal d0-d4 of latch circuit 23. On the other hand, outputs of output terminals Q0-Q3 of counter 21 are applied to AND circuits G0-G3 receiving the output of circuit 23 and while counter 21 counts up and resets once, the parallel output of circuit 23 is converted into series data successively, which is supplied to transistor TR1, so that the parallel signal will be converted into a series sigeasily.
申请公布号 JPS6246913(B2) 申请公布日期 1987.10.05
申请号 JP19790150457 申请日期 1979.11.20
申请人 RICOH KK 发明人 MIZUTA TOSHIAKI
分类号 H03M9/00;G06F5/06;G08C19/28;H04L25/38 主分类号 H03M9/00
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