发明名称 OUTPUT BUFFER CIRCUIT
摘要 PURPOSE:To obtain an output buffer circuit from which no through-current flows by generating two signals with different rising falling points from one and same signal and controlling TRs so that one TR is cut off before the other is turned on. CONSTITUTION: An output signal F from an AND circuit 6 is retarded by a prescribed quantity at a delay circuit 9 and a signal G is obtained. An OR signal H and an AND signal J between signals F,G are obtained respectively by an OR circuit 7 and an AND circuit 8, but the waveforms of them are unsharpened. Gates of a PMOS l and an NMOS 2 are controlled respectively by the signals H,J and the PMOS 1 and the NMOS 2 are turned on/off respectively shown in figure. Even when the PMOS 1 is turned off, so long as the NMOS 2 is not turned on, the potential level of the output point 3 is kept to logical 1, and even when the NMOS 2 is turned off, so long as the PMOS l is not turned on, the potential level of the output point 3 is kept to logical 0 and the signal waveform is as shown in figure K. Since the PMOS l and the NMOS 2 are not turned on simultaneously, no through-current flows.
申请公布号 JPS62225026(A) 申请公布日期 1987.10.03
申请号 JP19860071743 申请日期 1986.03.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUGINO HIROYUKI
分类号 H03K17/687;H03K19/00;H03K19/0185;H03K19/0948 主分类号 H03K17/687
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