| 摘要 |
PURPOSE:To enhance output accuracy even if there is not only an error in assembling accuracy but also a play in a speed reducer, by providing a reference signal to a first stage code plate and making the detection signals of code plates on and after the second stage synchronous. CONSTITUTION:Code plats 10, 11 are connected through a speed reducer 12 and a speed reducing ratio is set to 1/2. The codes of the first halves of first-third bits S1, S2, S3 are written in the code plate 10 directly connected to an input shaft 13 and all of fourth and fifth bits S4, S5 are written in the code plater 11. A transfer code T1 (one wherein the second bit S2 is advanced by a 1/4 period) is written in the code plate 10 as a reference signal, and codes F4, F5 advanced by (a) in a phase from the original position of a code desired to be outputted and codes B4, B5 delayed by (a) in a phase are respectively written in the code plate 11 at every code desired to be outputted. Both code plates 10, 11 are located so that the rising of the transfer code T1 comes between the codes F1, F2 and the codes B4, B5. |
