发明名称 |
PHASE ERROR DETECTION CIRCUIT |
摘要 |
PURPOSE:To attain a fast phase locking by deciding a detected phase at plural regions and changing the phase of a reference timing signal based on the result so as to eliminate the increase in the detection error caused at the phase error of nearly + or -pi. CONSTITUTION:The 1st recovery timing signal 2 is retarded by 1/2 of the transmission rate at the 2nd delay circuit 17 to generate a comparison signal 18, which is compared with the 1st transmission rate frequency component 5 at the 2nd latch circuit 16 to apply phase decision. The phase decision signal 13 switches the phase of the 1st recovery timing signal 2 in an EX-OR circuit 15 to generate the 2nd recovery timing signal 14. A demodulated base band signal 1 is inputted to the 1st latch circuit 9 and the 2nd recovery timing signal 14 extracts the 2nd transmission rate frequency component 6 including the phase error information and the recovered base band signal 4. A substraction circuit 12 subtracts the 2nd transmission rate frequency component 6 from the 1st transmission rate frequency component 5 to extract a phase error signal 7. |
申请公布号 |
JPS62224137(A) |
申请公布日期 |
1987.10.02 |
申请号 |
JP19860065867 |
申请日期 |
1986.03.26 |
申请人 |
TOSHIBA CORP |
发明人 |
KUDO KYOICHI;SUZUKI HIDEO |
分类号 |
H03K5/00;H03K5/26;H04L7/02 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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