发明名称 COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To form a second layer wiring having no leak by a method wherein the side surfaces of a gate electrode are formed in such a way as to make an angle of nearly 90 deg. with the surface of a substrate and the side surfaces of a first layer wiring are formed in such a way as to make an acute angle with the substrate surface. CONSTITUTION:A first layer wiring 14 is formed of a tungsten layer of 4,000Angstrom , the same thickness as that of a gate electrode 13. The side surfaces 15 of the first layer are wiring are formed in such a way as to form an acute angle with a semi-insulative gallium-arsenic substrate 11. Metal 41 for a second layer wiring is left behind an interlayer insulating film 29 in a gate electrode part 23, but the parts of shadows are not formed on the interlayer insulating film in the first layer wiring part. Therefore, no leak is generated between a second layer wiring 25 and another second layer wiring 26. There is a possibility that the metal for a second layer wiring is left on parts 28 in the gate electrode part, but the metal for a second layer wiring is not left on parts 29. Therefore, no leak is generated between a second layer wiring 27 and the second wiring layer 26. Moreover, by forming the side surfaces 16 of the gate electrode in such a way as to become vertical to the substrate surface, the efficiency of the field-effect transistor can be accurately controlled.
申请公布号 JPS62224947(A) 申请公布日期 1987.10.02
申请号 JP19860067361 申请日期 1986.03.27
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 KATANO FUMIAKI
分类号 H01L21/3205 主分类号 H01L21/3205
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