| 摘要 |
<p>PURPOSE:To perform a correct reading test in a verify mode by providing a discharge circuit for discharging a charge stored in the stray capacity of a data line while the writing operation is completed and the verify mode is started in the data line or a common data line. CONSTITUTION:In order to realize the verify mode of high reliability, the MOSFETQ 16 of N channels is provided between the input terminal of a sense amplifier SA and the earth potential of the circuit. An internal timing signal Vr is supplied to the gate of this MOSFETQ 16. Accordingly, the MOSFETQ 16, while the internal timing signal Vr goes to a high level, namely immediately after the writing to a memory cell is completed, is turned on during the delay time td of a delay circuit and discharges the charge of the stray capacity Cf of the data line D1 through the common data line CD.</p> |
