| 摘要 |
<p>PCT No. PCT/SE87/00437 Sec. 371 Date May 17, 1988 Sec. 102(e) Date May 17, 1988 PCT Filed Sep. 28, 1987 PCT Pub. No. WO88/02513 PCT Pub. Date Apr. 7, 1988.A data processing system which executes two instruction sequences in an order determined in advance. With the aid of instructions, a main memory common to both sequences is activated for data information reading/writing. Increased data handling capacity is achieved in the following manner: both sequences are executed in parallel to start with. During execution of the first sequence, the main memory is prevented from being activated for writing due to the second sequence write instructions. A write address and data information included in a write instruction associated with the second sequence are intermediately stored. The intermediately stored write address is compared with the read addresses of the second sequence, and data information is prevented from being read from the main memory in response to an identity of the addresses, the intermediately stored data information being read instead. An address included in a read instruction associated with the second sequence is intermediately stored if this address has not been previously selected in conjuction with a write instruction associated with the second sequence. The intermediately stored read address is compared with the write address of the first sequence and execution of the second sequence is restarted in response to an identity of the addresses.</p> |
