发明名称 DIGITAL EQUALIZER
摘要 PURPOSE:To increase the equalization delay with simple constitution by converting an analog reception signal such as a voice signal including transmission distortion into a digital signal, converting the digital signal into a signal of a frequency region, multiplying a value equalizing the transmission distortion and dividing the equalizing processing restoring the multiplied output signal into a signal of time region into plural steps. CONSTITUTION:An analog reception signal is converted into a digital signal by an A/D converter 1, the digital signal is distributed by a demultiplexer 2 at each prescribed period and the result is fed sequentially to equalization processing blocks 3-1-3-4. Each equalization processing block applies the high speed Fourier transformation to the digital signal to obtain a signal of the frequency region, n-set of 0s are added to the tail end of the signal and the value equalizing the transmission distortion is multiplied. The high speed Fourier inverse transformation is applied to the multiplied output signal to form a signal of the time region. Through the equalizing processing above, even a signal with a large delay is outputted without rounding off at the conversion from the frequency to the time region and added to a signal in the same time. Thus, the equalization of large delay is attained without causing waveform distortion.
申请公布号 JPS62222721(A) 申请公布日期 1987.09.30
申请号 JP19860052946 申请日期 1986.03.11
申请人 FUJITSU LTD 发明人 KOBAYASHI NOBORU;OGAWA YOSHIHIKO;TAKAHASHI TAMAKI;KARIBE HIROHISA;KANEKO KAZUHIRO
分类号 H04B3/06 主分类号 H04B3/06
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