Address translation circuit.

摘要

An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffer is selected for use at the time a memory access depending on a signal (6) supplied from a processing unit (1) to indicate whether the memory access is related to an instruction cycle or an operand cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.