发明名称 Variable delay line system
摘要 This variable delay line system includes a variable delay line which has two output ends and a plurality of signal input points at its intermediate points, a means for selecting one of the input points of the variable delay line and for inputting a signal thereto, and a means for switching the signals from the output ends of the variable delay line and for outputting them. Optionally, a fixed delay line can further be included. Thereby, the varibale delay line system has a simple and compact structure and is effective.
申请公布号 US4697162(A) 申请公布日期 1987.09.29
申请号 US19860826374 申请日期 1986.02.05
申请人 ELMEC CORPORATION 发明人 KAMEYA, KAZUO
分类号 H01P9/00;H03H7/34;(IPC1-7):H01P9/00;H01P3/08 主分类号 H01P9/00
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