| 摘要 |
PURPOSE:To output a correct voltage value though the operation start time is different between transfer switches, by inserting a make switch, whose operation is started at a little bit delay from the operation start of each transfer switch, between the transfer switch and an output terminal. CONSTITUTION:When a driving signal is inputted to a transfer switch driving circuit 16, transfer switches 13a and 13b are connected to normally open terminal sides. Make switches 15a and 15b are closed by a make switch driving circuit 17 when a prescribed time elapses after transfer switches 13a and 13b are connected there, and the voltage of a capacitor 12 is outputted to output terminals 14a and 14b. Since said delay time is made longer than the time difference of operation start between transfer switches 13a and 13b, the formation of a common mode current circuit is prevented and a correct voltage value is outputted.
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