| 摘要 |
<p>PURPOSE:To easily control the stop state of a CPU and to simplify the constitution of a control circuit by stopping the clock of the CPU when an access is given to the peripheral device of low speed or a halt mode is attained for a stand-by function. CONSTITUTION:When a halt instruction is executed in the halt mode and in the stop mode of a CPU, the halt signal is outputted from an instruction decoder 22. Thus the output of a latch 50 is set at 1 in the next cycle, therefore CCK is set at 1 and the CPU is stopped. Then a halt mode is secured. When an interruption request signal INT is inputted during the halt mode, an RS flip-flop 58 is reset by the SCKB timing and the output of the flip-flop 58 is st at 0. Then the output of the latch 50 is set to 0 from the SCK timing of the next machine cycle. Thus the CCK, CCKB and CCKS are outputted in a normal way. As a result, the CPU is stopped even in a halt mode by stopping the result, the CPU is stopped even in a halt mode by stopping the clock of the CPU.</p> |
