| 摘要 |
PURPOSE:To perform the logical simulation at high speed by collecting gates at every transmission address of gate signal to perform the logic operation and transmission of signals. CONSTITUTION:When a logic designer uses gates 11, 12, 13 and 14 to simulate the logic circuits connected by full lines, a logic simulator connects the fixed output gates 15 and 16 which supply the fixed signal value to the gate of the designer to the logic circuits of the designer by broken lines in response to each input terminal. Then plural gates are added to supply the fixed signal value that gives no effect to the gate produced by the designer. Thus the logic simulation is carried out. At the same time, plural reading actions are avoided to the same address. In such a way, a logic circuit can be simulated at high speed.
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