发明名称 LOGIC CIRCUIT
摘要 PURPOSE:To form an exclusive OR or non-exclusive OR logic circuit comprising simple constitution where the numbers of elements and gates are reduced by using 2 N-channel circuit blocks and 2 P-channel circuit blocks. CONSTITUTION:When lines X, Y are at (0, 0), transistors (TRs) TN2, TP2 are turned on and TRs TP1, TN1 are turned off and an output node goes to 0 while being drawn by X. When the lines X, Y are at (0, 1), the TRs TN1, TP1 are turned on and the TRs TP2, TN2 are turned off and the output goes to 1. When the lines X, Y are at (1, 0), the TRs TP2, TN2 are turned on and the TRs TN1, TP1 are turned off, the output goes to 1. When the X, Y at the (1, 1), the TRs TN1, TP1 are turned on and the TRs TN2, TP2 are turned off and the output node goes to 0. In the operation above, the signals X, the inverse of X are replaced and TRs QN1, QN2 are replaced by the circuit change, then the exclusive OR logic is changed into the non-exclusive OR logic.
申请公布号 JPS62220028(A) 申请公布日期 1987.09.28
申请号 JP19860064604 申请日期 1986.03.20
申请人 FUJITSU LTD 发明人 SUZUKI ATSUSHI;NAGASHIMA MASAJI
分类号 H03K19/0948;H03K19/21 主分类号 H03K19/0948
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